The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for an advanced array local clock buffer base block circuit.
High performance arrays, such as a static random access memory (SRAM), normally require dock generation circuits to control internal circuit timings. These clock generation circuits (also known as Local Clock Buffers (LCBs)) are used to control array word decode/bit decode and read/write critical circuit functions. To provide timing tuning flexibilities as well as hardware debug capabilities, state of the art array LCBs often have programmable controls on its clock delay or pulse width circuits. Multiple discrete timing settings of delay or pulse width are implemented with explicit decoders and with typical inverter delay chains. Such programmability of timing settings of delay or pulse width however adds circuit complexity, chip area and power consumption to the LCB structures. A state of the art local dock control buffer is constructed with modular circuit blocks. This modular topology makes the design extremely flexible to drive different clock loads and latch types.
An array LCB uses the common logical base block used for all LCB applications on the chip. Such an array LCB also has additional devices in the feedback path to vary the pulse with of the output clock signal (clk). A short cycle time of 184 picoseconds and a high mid cycle uncertainty of 18 picoseconds creates massive race between rising negative active global dock signal (nclk) and the feedback path signal (fb_2). That is, the pulse width of the output clock signal (clk) is no long determined by the feedback path signal but by the nclk rising edge. This makes the array LCB output pulse width vary over nclk frequency which is very critical for array applications.
To guarantee a cycle-time independent pulse width over different cycle times, big devices are required in the array LCB feedback path to ensure that the feedback path is always faster than the fastest nclk situation. Further, cycle stealing is required inside the array LCB to overcome the race between feedback path and the rising nclk. The state of the art array LCB only works in default delay and pulse width settings and big devices in the array LCB feedback path significantly increase the area required for such array LCBs.